DS200SDCCG1AEC DS215SDCCG1AZZ01A card spare parts in stock
Technical data of product parameters
CCR). The input channels are sampled consecutively, starting with Channel 00
located at the bottom (lowest address) of each block in the buffer, and proceeding
through the highest channel at the top of the block.
The total address space of the VMIVME-3122 is 4096 bytes. Memory located at offset
address $0880 to DS200SDCCG1AEC DS215SDCCG1AZZ01A is available as on-board scratch pad memory.
Data Storage and Retrieval
The data buffer can be loaded or read from the bus at any time. Arbitration for the
buffer occurs at the beginning of an update from the DS200SDCCG1AEC DS215SDCCG1AZZ01Aconverter. If the converter
has control of the memory when a bus transfer is initiated, the transfer will be
extended by approximately 250 nsec while the buffer update is completed.
DS200SDCCG1AEC DS215SDCCG1AZZ01Aa bus transfer is in progress when a converter access is requested, the bus transfer
will proceed normally and the converter access will take place after the transfer has
been completed.
A data ready flag can be programmed to occur at the end of the buffer, or can beDS200SDCCG1AEC DS215SDCCG1AZZ01A
programmed to occur at the middle of the buffer. The data ready flag can initiate an
interrupt request, or can be read from the bus as a status flag.
Operating Modes
All operating modes available with the VMIVME-3122 are controlled through the
Control and Status Register (CSR) and the Configuration Control Register (CCR). The
operating modes are a combination of trigger modes from the CSR and scan mode
from the CCR. Operating modes are described in detail in Chapter 3, and are
summarized here as trigger and scan modes:
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