HONEYWELL 51405040-175 CC-PDIL01 Automatic industrial control spare parts inventory

HONEYWELL 51405040-175 CC-PDIL01 Automatic industrial control spare parts inventory

Technical data of product parameters

Word address 13 (D in Hex) is used to write to the Module Configuration Register 51405040-175 CC-PDIL01
and to read the Module Status Register. The status register can be read by using the
Point Information window at an Operator Station (see the Bit Pattern Field on the
Hardware Tab).This bit is the result of a checksum test of the EEPROM. A failure of this
test can indicate a bad EEPROM, but typically indicates that the module
has not been calibrated. A “0” indicates that there is no error condition.
If this error is present, the error will be indicated by the module error
LED being lit and the module will not process the point information.
The point fault bit will also be set as all the point data is uncalibrated.
When this error is present, no other processing takes place. The “1” state
of this bit indicates an unrecoverable error condition in the field.
Bit 8: This bit indicates whether the on-board integrating timebase is 80 msec
(4 line cycles of a 50 Hz system) or 83.3 msec (5 line cycles of a 60 Hz
system). A “0” indicates that the timebase is 83.3 msec (60 Hz line frequency) and is the default setting. 51405040-175 CC-PDIL01
Bit 9: This bit indicates whether to use the line frequency tracking if it is
present. A write of “1” indicates to use the tracking input. A read of “1”
indicates that the module is using the tracking input. The default state isThis bit indicates whether the line frequency tracking signal is present and active for greater normal and common mode rejection. A “0” indicates that the line frequency tracking signal is NOT present.
Bit 11: This bit indicates whether the hardware EEPROM PE signal is active. A 51405040-175 CC-PDIL01
“0” indicates that the module is in normal operating mode and calibration and ID programming commands will not be processed.
Bit 12: This bit reflects the detection of the internal 625 KHz PSD signal at
module initialization. This verifies that the multifunction FPGA and the
microcontroller’s timer 0 are functioning. A “0” indicates that there is no
error condition. A “1” indicates an unrecoverable error condition in the
field.

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