ABB 3BHE019633R0101 PDD200A101 module

ABB 3BHE019633R0101 PDD200A101 module

Technical data of product parameters

not programmed with aligned source 3BHE019633R0101 PDD200A101 and destination addresses and an attempt to start the DMA is made, the DMA will not start, it will set the protocol error bit (P_ERR) in the DCSR register, and if enabled to, generate an interrupt. The user must reprogram the source and destination address registers 3BHE019633R0101 PDD200A101 before each transfer. These registers are not updated automatically. If read during DMA activity, they will return the number of bytes remaining to transfer on the PCI side. All of the DMA registers are locked against any changes by the user while the DMA is active. When stopped due to an error situation, the DLA and DVA registers should not be used, but the DTBC is valid. Transfer Size The DMA may be programmed through the DMA Transfer Byte Count register (DTBC register in Table B-100) to transfer any number of bytes from 1 byte to 16 Mbytes. There are no alignment requirements to the source or destination addresses. Should the width of the data turnovers (8- through 64-bit on VMEbus and 32- or 64-bit on PCI) not align to the length of the transfer or the source/destination addresses, the3BHE019633R0101 PDD200A101 will insert transfers of smaller width on the appropriate bus. For example, if a 15-byte transfer is programmed to start at address $1000 on the VMEbus, and the width is set for D32, the DMA will perform three D32 transfers, followed by a D16 transfer, followed by a D08 transfer. The Universe II does not generate unaligned transfers. On a 32-bit PCI bus, if the start address was $2000, the DMA would generate three data beats with all byte lanes enabled, and a fourth with three byte lanes enabled.The 3BHE019633R0101 PDD200A101 register is not updated while the DMA is active (indicated by the ACT bit in the DGCS register). At the end of a transfer it will contain zero. However, if stopped by the user (via the STOP bit in the DGCS register) or the DMA encounters an error, the DTBC register contains the number of bytes remaining to transfer on the source side

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