ABB 3BHE020356R0101-GFD212A industrial control module card
Technical data of product parameters
Starting the DMA while3BHE020356R0101-GFD212A will result in one of two situations. If the CHAIN bit in the DGCS register is not set, the DMA will not start; it will perform no action. If the CHAIN bit is set, then the DMA loads the DMA registers with the contents of the command packet pointed to by the DCPP register. Note that the DCPP[31:5] field of the 3BHE020356R0101-GFD212Aregister implies that the command packets be 32-byte aligned (bits 4:0 of this register must beThe width of the transfer is set with the VDW field in the DCTL register. The VCT bit determines whether or not the Universe II VMEbus Master will generate BLT transfers. The value of this bit only has meaning if the address space is A24 or A32 and the data width is not 64 bits. If the data width is 64 bits the Universe II may perform MBLT transfers independent of the state of the 3BHE020356R0101-GFD212A bit. The Universe II may perform data transfers smaller than that programmed in the VDW field in order to bring itself into alignment with the programmed width. For example if the width is set for D32 and the starting VMEbus address is 0x101, the DMA will perform a D08 cycle followed by a D16 cycle. Only once it has achieved the alignment set in the VDW field does it start D32 transfers. At the end of the transfer, the DMA will also have to perform more low-width transfers if the last address is not aligned to VDW. Similarly, if the 3BHE020356R0101-GFD212Abit is set to enable block transfers, the DMA may perform non-block transfers to bring itself into alignment. On the PCI bus, the DMA provides the option of performing 32- or 64-bit PCI transactions through the LD64EN bit in the DCTL register If the Universe II has powered-up on a 32-bit bus, this bit will have no effect. If powered-up on a 64-bit bus, this bit can provide some performance improvements when accessing 32-bit targets on that bus.
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