PM3328B-6-1-3-E power module

PM3328B-6-1-3-E power module

Technical data of product parameters

When the VMEbus requests local bus mastership and the PM3328B-6-1-3-E
is the current local bus master and it is executing a cycle that
requires the VMEbus, then a dual port lockup condition occurs and
the VMEchip signals a retry to the MC68030 by activating the
BERR* and HALT* signal lines together. The MC68030 responds by
aborting the current cycle, at which time it relinquishes local bus
mastership so that the PM3328B-6-1-3-Emultiport arbiter can grant it to the
VMEbus. When the VMEbus has finished with the DRAM, the GCC
multiport arbiter returns local bus mastership to the MC68030 and
it retries the cycle that was aborted to allow the dual port access. When the LANCE needs to access DRAM it requests local bus mastership from the GCC multiport arbiter. When granted, the
LANCE performs up to 16 DRAM accesses, then gives up local bus
mastership. If a parity error occurs while enabled, the DRAM
controller indicates it by not activating LANRDY* to thePM3328B-6-1-3-E
The LANCE sees this as a memory fault and gives up local bus
mastershipWhen parity checking is enabled, the current bus master receives a bus error (or no LANRDY*, if LANCE) if it is accessing the local
DRAM and a parity error occurs. If the MC68030 is the local bus
master when the parity error occurs, the Parity Error (PE) status bit
is set in the PCC status register. Note that this bit is only useful if
mode 3 parity checking is set. If mode 2 parity checking is set, the
MC68030 is not able to read status after the occurrence of the parity
error. An interrupt can happen during the execution of the bus
error handler (before an instruction can write to the status
register to raise the interrupt mask). If the PM3328B-6-1-3-E interrupt service
routine causes a second bus error, the status that indicates the
source of the first bus error may be lost. The software must be
written to deal with this. The PCC can be programmed to
generate a Level 7 interrupt when a bus error occurs. This
may help force the MC68030 to a known place when a bus
error occurs.
❏ The PCC can take a VMEbus bound BERR* (which updates
the status bits) between the MC68030 receiving and handling
of a bus error, or vice-versa.

Product picture display

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