BENTLY NEVADA 133442-01 I/O module card

BENTLY NEVADA 133442-01 I/O module card

Technical data of product parameters

The MC68030 performs operations that require indivisible cycle
sequences to the local DRAM and to the VMEbus. The 133442-01
requires special circuitry to support these operations. Indivisible
accesses to a single address are called Single Address Read-ModifyWrite Cycles (SARMC). Indivisible accesses to multiple addresses
are called Multiple Address Read-Modify-Write Cycles (MARMC).
SARMC cycles (caused by Test and Set (TAS) and single byte
Compare and Swap (CAS) instructions) are supported fully by the
MVME147. This is possible because the VMEbus defines such
cycles. 133442-01
MARMC cycles (caused by CAS2 and multi-byte CAS instructions
and by MMU table walking) are conditionally supported by the
133442-01. The VMEbus does not define these cycles.
The WAITRMC bit in the PCC controls the support of MARMC
cycles. If WAITRMC is cleared, MARMC cycles are not guaranteed
to be indivisible. Furthermore, if MARMC cycles straddle onboard
DRAM and VMEbus memory, the MVME147 malfunctions.
If WAITRMC is set, MARMC cycles are guaranteed to be indivisible
only if the other VMEbus board implements its MARMC cycles the
same way as the MVME147 (with WAITRMC set). Note that setting
the WAITRMC bit can be a performance penalty. When the bit is
set, the 133442-01 waits to become VMEbus master before it
executes any MARMC cycle (even though it may be going only to
onboard DRAMThe EIA-232-D standard is the most common terminal/computer
and terminal/modem interface, and yet it is not fully understood.
This may be because not all the lines are clearly defined, and many
users do not see the 133442-01need to follow the standard in their
applications. Often designers think only of their own equipment,
but the state of the art is computer-to-computer or computer-tomodem operation. A system should easily connect to any other system

Product picture display

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Introduction to main products

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reminder

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