ABB SDCS-PIN-51 Governor Detection BoardPP836A 3BSE042237R2 boost operation panel

ABB PP836A 3BSE042237R2 boost operation panel

Technical data of product parameters

In order to provide for a bumpless changeover with respect to the control network,
both the MAC and IP addresses are swapped between the initial primary and backup PP836A 3BSE042237R2
CPUs. The addresses of the initial primary CPU are stored and kept as the addresses
used by the acting primary CPU. Similarly the addresses of the initial backup CPU
are stored to be used by the acting backup CPU. This means that a redundant
controller will be always identified and recognized by the same addresses regardless
of which CPU module actually acting as primary.• Oscillator supervision
• CRC on firmware and data storage
An SM811 operates like an SM810 for SIL2 but can also together with the PP836A 3BSE042237R2
form a controller compliant with SIL3 according to IEC61508, certified by TÜV.
The ModuleBus telegrams used in a High Integrity system with the S800 High
Integrity modules use the concept of long frames. Long frames are ModuleBus
telegrams that are extended with a safety header, comprising additional diagnostics
data and CRC32. S800 ModuleBus telegrams sent to the S800 I/O High Integrity PP836A 3BSE042237R2
modules uses data from the PM865 and an inverted CRC32 from the
SM810/SM811. The I/O module checks that the safety header is correct. Data
received from the S800 I/O High Integrity modules over the ModuleBus have the
safety header independently verified by both SM810/SM811 and PM865. Any
CRC32 or other faults in the safety header will result in a retry transmission and, if
repeated, a shutdown of the faulty S800 I/O High Integrity module.

Product picture display

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