GE V7768 320000 module card

GE V7768 320000 module card

Technical data of product parameters

Each timer can be independently enabled by writing a “1” to the appropriate “Timer x
Enable” field. Similarly, the generation of interrupts by each timer can be V7768 320000
independently enabled by writing a “1” to the appropriate “Timer x IRQ Enable”
field.
If an interrupt is generated by a timer, the source of the interrupt may be determined
by reading the “Timer x Caused IRQ” fields. If the field is set to “1”, then the
respective timer caused the interrupt. Note that multiple timers can cause a single
interrupt. Therefore, the status of all timers must be read to ensure that all interrupt V7768 320000
sources are recognized.
A particular timer interrupt can be cleared by writing a “0” to the appropriate “Timer
x Caused IRQ” field. Alternately, a write to the appropriate Timer x IRQ Clear (TxIC)
register will also clear the interrupt. When clearing the interrupt using the “Timer x
Caused IRQ” fields, note that it is very important to ensure that a proper bit mask is
used so that other register settings are not affected. The preferred method for clearing V7768 320000
interrupts is to use the “Timer x IRQ Clear” registers described below.The “Read Latch Select” bit is used to select the latching mode of the programmable
timers (See “Timers” section above). If this bit is set to “0”, then each timer output is
latched upon a read of any one of its address. For example, a read to the TMRCCR12
register latches the count of timers 1 and 2. A read to the TMRCCR3 register latches
the count of timer 3. This continues for every read to any one of these registers.

Product picture display

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reminder

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