GE VMIVME-1128 PLC module In Stock details

GE VMIVME-1128 PLC module In Stock details

Technical data of product parameters

The PPC Arbiter supports two prioritization schemes. Both schemes affect VMIVME-1128
the priority of the CPU’s with respect to each other. The CPU fixed option
always places the priority of CPU0 over CPU1. The CPU rotating option
gives priority on a rotational basis between CPU0 and CPU1. In all cases,
the priority of the CPUs remains fixed with respect to the priority of
HAWK and EXTL, with HAWK always having the highest priority of all.
The PPC Arbiter supports four parking modes. Parking is implemented
only on the CPUs and is not implemented on either HAWK or EXTL. The VMIVME-1128
parking options include parking on CPU0, parking on CPU1, parking on
the last CPU, or parking disabled.
There are various system level debug functions provided by the PPC
Arbiter. The PPC Arbiter has the optional ability to flatten the PPC60x bus
pipeline. Flattening can be imposed uniquely on single beat reads, single
beat writes, burst reads, and burst writes. It is possible to further qualify the VMIVME-1128
ability to flatten based on whether there is a switch in masters or whether
to flatten unconditionally for each transfer type. This is a debug function
only and is not intended for normal operation.The PHB generates data parity whenever it is sourcing PPC data. This
happens during PPC Master write cycles and PPC Slave read cycles. Valid
data parity is presented when DBB_ is asserted for PPC Master write
cycles. Valid data parity is presented when TA_ is asserted for PPC Slave
read cycles.

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