AB Rockwell 1746-OB32 PLC controller in stock
Technical data of product parameters
a Big 1746-OB32Endian processor writes its least significant byte in the highest byte address in memory, while its most significant byte is written to the lowest address. The converse is true during read operations: the data in the lowest byte address is considered to be the most significant, while the byte in the highest address is considered to be the least significant.The 1746-OB32VMEbus Specification does not specify which byte of a multiple-byte transfer is most significant. The VMEbus Specification does, however, require certain byte lanes to be associated with certain byte addresses. As shown in Table 1-1 on page 31, byte(0) must be transferred on data lines D31-D24 during a Lword transfer while byte(3) must be transferred on lines D7-D0. This byte and address alignment is exactly the same as that for a Big Endian processor such as the Motorola 68040. If a Little Endian device were to have its data bus directly connected to the VMEbus (i.e., D31 to D31, D30 to D30, etc.), then the 1746-OB32 most significant byte data supplied to the VMEbus D31-D24 byte lane during a Lword write would be stored by the VMEbus in the lowest of the four destination byte addresses – opposite that expected by the Pentium microprocessor. This poses no problem if the 32-bit value written is always read back using a similar Lword transfer (i.e., all four bytes at once), since the swapped data gets swapped again and appears to the Host exactly as it should. However, if 1746-OB32the data written by the 32-bit Lword transfer were to be retrieved using any other method, for example, using four separate byte transfers creates a problem. The data at the lowest byte address would be incorrectly assumed to be the least significant, while it is actually the most significant
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