ABB 81943A041-1 inventory module

ABB 81943A041-1 inventory module

Technical data of product parameters

Upon completion of a prefetched read transaction, any residual read data
left within the PCI FIFO will be invalidated (discarded). The PHB does not 81943A041-1
have a mechanism for snooping the PPC60x bus for transactions
associated with the prefetched read data within the PCI FIFO, therefore
caution should be exercised when using the prefetch option within
coherent memory space.
The PPC Master will never perform prefetch reads beyond the address
range mapped within the PCI Slave map decoders. As an example, assume
PHB has been programmed to respond to PCI address range $10000000 81943A041-1
through $1001FFFF with an offset of $2000. The PPC Master will perform
its last read on the PPC60x bus at cache line address $3001FFFC or word
address $3001FFF8.
The PPC60x bus transfer types generated by the PPC Master depend on the
PCI command code and the INV/GBL bits in the PSATTx registers. The
GBL bit determines whether or not the GBL_ signal is asserted for all
portions of a transaction and is fully independent of the PCI command
code and INV bit. A following table shows the relationship between the
PCI command codes and the INV bit.The PPC master incorporates an optional operating mode called Bus Hog.
When Bus Hog is enabled, the PPC master will continually request the
PPC bus for the entire duration of each PCI transfer. When Bus Hog is not 81943A041-1
enabled, the PPC master will structure its bus request actions according to
the requirements of the FIFO. The Bug Hog mode was primarily designed
to assist with system level debugging and is not intended for normal modes
of operation. It is a brute force method of guaranteeing that all PCI to
PPC60x transactions will be performed without any intervention by host
CPU transactions. Caution should be exercised when using this mode since
the over-generosity of bus ownership to the PPC master can be detrimental
to the host CPU’s performance. The Bus Hog mode can be controlled by
the XMBH bit within the GCSR. The default state for XMBH is disabled.

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