ABB CI868K01-eA 3BSE048845R2 communication module

ABB CI868K01-eA 3BSE048845R2 communication module

Technical data of product parameters

 The VMEchip allows software to program the interrupt handler
to generate a local interrupt after it concludes a CI868K01-eA 3BSE048845R2
cycle. The level of the local interrupt is shown in Table 4-6.
Setting the IACKEN control bit to 1 enables the IACK interrupt.
This function is intended to be coupled with the use of the
VMEchip global interrupt function. If this bit is set, a local
interrupt (to the MC68030) is generated when a VMEbus IACK
cycle acknowledges the interrupt (refer to the Interrupt Request
Register section in this chapterAs described in the Programming the GCSR section in thisCI868K01-eA 3BSE048845R2
chapter, the GCSR provides four location monitors. Two of
them, location monitor 0 and 1, cause a local interrupt when the
VMEbus address they are configured to monitor is accessed.
The LM1EN control bit allows software to mask the interrupt
requested when an access is detected to the address monitored
by location monitor 1. The level of local interrupt is shown in
Table 4-6. Setting the LM1EN bit to 1 unmasks the interrupt.
Bit 5 As described in the Programming the GCSR section in this
chapter, the GCSR provides a global high priority attention
interrupt bit SIGHP which allows other VMEbus masters to
interrupt the MC68030. The level of the local interrupt is shown
in Table 4-6. Setting the SIGHEN control bit to 1 unmasks the
SIGHP interrupt.CI868K01-eA 3BSE048845R2
Bit 6 Setting SFIEN to 1 enables a low level on the VMEbus SYSFAIL*
line to cause an interrupt to the MC68030. The level of the
SYSFAIL* interrupt is shown in Table 4-6.
Bit 7 The VMEchip allows software to configure the VMEbus master
to operate in a write posted mode (i.e., acknowledge the
MC68030 VMEbus bound write cycle before it has actually been
executed on the VMEbus). If the VMEchip encounters a
VMEbus bus error as it attempts to complete the write posted
cycle, the VMEchip notifies the MC68030 via Level 7 interrupt if
the WPERREN bit is set. CI868K01-eA 3BSE048845R2
The utility interrupt vector register provides the local
CPU with a unique vector for each of the utility
interrupts. Close examination reveals that the assigned
level of each of the utility interrupts, as defined in the
Utility Interrupt Mask Register section in this chapter, is
the same as its assigned ID. This is implemented by
reflecting

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