ABB PPC907BE 3BHE024577R0101 module controller

ABB PPC907BE 3BHE024577R0101 module controller

Technical data of product parameters

 Following the PPC907BE 3BHE024577R0101 specification, before a 64-bit PCI initiator starts a 64-bit transaction, it engages in a protocol with the intended target to determine if it is 64-bit capable. This protocol typically consumes one clock period. To save bandwidth, the LD64EN bit can be cleared to bypass this protocol when it is known that the target is only 32-bit capableThe DMA Command Packet Pointer PPC907BE 3BHE024577R0101 in Table 3-16 on page 75) points to a 32-byte aligned address location in PCI Memory space that contains the next command packet to be loaded once the transfer currently programmed into the DMA registers has been successfully completed. When it has been completed (or the PPC907BE 3BHE024577R0101 register is zero when the GO bit is set) the DMA reads the 32-byte command packet from PCI memory and executes the transfer it describes. DMA Initiation Once all the parameters associated with the transfer have been programmed (source/ destination addresses, transfer length and data widths, and if desired, linked lists enabled), the DMA transfer is started by setting the GO bit in the DGCS register. This causes the DMA first to examine the DTBC register. If it is non-zero, it latches the values programmed into the PPC907BE 3BHE024577R0101 and DVA registers and initiates the transfer programmed into those registers. If DTBC=0, it checks the CHAIN bit in the DGCS register and if that bit is cleared it assumes the transfer to have completed and stops. Otherwise, if the CHAIN bit is set, it loads into the DMA registers the command packet pointed to by the DCPP register and initiates the transfer described there. If the GO bit is set,

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