ABB static converter PHARPS32200000 F8-G2B9B3B6

ABB static converter PHARPS32200000 F8-G2B9B3B6

Technical data of product parameters

The HSC differs from the PHARPS32200000 F8-G2B9B3B6 and CTD counters. The CTU and CTD are
software counters. The HSC is a hardware counter and operates
asynchronously to the ladder program scan. The HSC accumulated value
(C5:0.ACC) is normally updated each time the HSC rung is evaluated in the
ladder program. This means that the HSC hardware accumulator value is
transferred to the HSC software accumulator. Only use the OTE instruction
to transfer this value. The HSC instruction immediately clears bit C5:0/UA
following the accumulated update.
Many HSC counts may occur between HSC evaluations, which would make
C5:0.ACC inaccurate when used throughout a ladder program. To allow for an PHARPS32200000 F8-G2B9B3B6
accurate HSC accumulated value, the update accumulator bit (C5:0/UA)
causes C5:0.ACC to be immediately updated to the state of the hardware
accumulator when set.
Use the RES instruction to reset the high-speed counter at address C5:0. The
HSC instruction clears the status bits, the accumulator, and loads the preset
value duringIn the following figures, rungs 1, 18, and 31 of the main program file each PHARPS32200000 F8-G2B9B3B6
consist of an XIC instruction addressed to the HSC done bit and a JSR
instruction. These rungs poll the status of the HSC done bit. When the Done
bit is set at any of these poll points, program execution moves to subroutine
file 3, executing the HSC logic. After the HSC logic is executed, the Done bit
is reset by an unlatch instruction, and program execution returns to the main
program fileUse the GEQ instruction to test whether one value (source A) is greater than
or equal to another (source B). If the value at source A is greater than or equal
to the value at source B, the instruction is logically true. If the value at source
A is less than the value at source B, the instruction is logically false.If the 16 bits of data at the source address are equal to the 16 bits of data at the
compare address (less masked bits), the instruction is true. The instruction
becomes false as soon as it detects a mismatch. Bits in the mask word mask
data when reset; they pass data when set.

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