ABB XVC767AE102 3BHB007209R0102 CPU module
Technical data of product parameters
The description of the CONFIG_DATA register is also presented in three XVC767AE102 3BHB007209R0102
perspectives; from the PCI bus, from the PPC Bus in Big Endian mode,
and from the PPC bus in Little Endian mode. Note that the view from the
PCI bus is purely conceptual, since there is no way to access the
CONFIG_DATA register from the PCI bus.This register is used to report the frequency (in Hz) of the clock source for
the global timers. Following reset, this register contains zero. The system XVC767AE102 3BHB007209R0102
initialization code must initialize this register to one-eighth the MPIC
clock frequency. For the PHB implementation of the MPIC, a typical value
would be $7de290 (which is 66/8 MHz or 8.25 MHz)BASE COUNT. This field contains the 31 bit count for
this timer. When a value is written into this register and
the CI bit transitions from a 1 to a 0, it is copied into the
corresponding Current Count register and the toggle bit in
the Current Count register is cleared. When the timer
counts down to zero, the Current Count register is
reloaded from the Base Count register and the timer’s
interrupt becomes pending in MPIC processingThere are four Interprocessor Interrupt Dispatch Registers. Writing to an
IPI Dispatch Register with the P0 and/or P1 bit set causes an interprocessor XVC767AE102 3BHB007209R0102
interrupt request to be sent to one or more processors. Note that each IPI
Dispatch Register has two addresses. These registers are considered to be
per processor registers and there is one address per processor. Reading
these registers returns zeros.There is one Task Priority Register per processor. Priority levels from 0
(lowest) to 15 (highest) are supported. Setting the Task Priority Register to XVC767AE102 3BHB007209R0102
15 masks all interrupts to this processor. Hardware will set the task register
to $F when it is reset or when the Init bit associated with this processor is
written to a on
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