ABSOLUTE MOX12-P3509 B 80026-173-23 controller

ABSOLUTE MOX12-P3509 B 80026-173-23 controller

Technical data of product parameters

While the PCI Slave is filling the PCI FIFO with write data, the PPC
Master can be moving previously posted write data onto the PPC60x bus.
In general, the PPC60x bus is running at a higher clock rate than the PCI 80026-173-23
bus, which means the PCI bus can transfer data at a continuous
uninterrupted burst while the PPC60x bus transfers data in distributed
multiple bursts. The PHB write posting mechanism has been tuned to
create the most efficient possible data transfer between the two busses
during typical operation. It is conceivable that some non-typical conditions
could exist that would upset the default write post tuning of the PHB. For 80026-173-23
example, if a PPC60x master is excessively using PPC60x bus bandwidth,
then the additional latency associated with obtaining ownership of the
PPC60x bus might cause the PCI Slave to stall if the PCI FIFO gets full. If
the PCI Slave is continuously stalling during write posted transactions,
then further tuning might be needed. This can be accomplished by
changing the WXFT (Write Any Fifo Threshold) field within the PSATTx
registers to recharacterize PHB write posting mechanism. The FIFO The PPC Master has an optional read ahead mode controlled by the RAEN
bit in the PSATTx registers that allows the PPC Master to prefetch data in
bursts and store it in the PCI FIFO. The contents of the PCI FIFO will then 80026-173-23
be used to satisfy the data requirements for the remainder of the PCI read
transaction. The PHB read ahead mechanism has been tuned for maximum
efficiency during typical operation conditions. If excessive latencies are
encountered on the PPC60x bus

Product picture display

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