ALSTOM AB121 module off the shelf
Technical data of product parameters
The MPIC is hosted by the PHB. A custom MPIC Interface is provided to
allow write data and control to be passed to the MPIC and to allow read AB121
data to be passed back to the PHB. The MPIC Interface is controlled
exclusively by the PCI Slave.
The data path function imposes some restrictions on access to the MPIC,
the PCI Registers, and the PPC Registers. The MPIC and the PCI Registers
are only accessible to PCI originated transactions. The PPC Registers are AB121
only accessible to PPC originated transactions.
PHB has several small blocks that support various PPC functions.
Arbitration is provide by the PPC Arbiter block. Cache line locking (via
PCI Lock) is handled by the PPC Lock block. Finally, a timer function is
implemented in the PPC Timer block.
PHB also provides miscellaneous support for various PCI functions.
Arbitration on the PCI bus is handled by the PCI Arbiter block. Parity
checking and generation is handled within the PCI Parity block.
PPC Bus Interface
The PPC Bus Interface is designed to be coupled directly to up to two
PPC601, PPC 603, or PPC604 microprocessors and one peripheral
PPC60x master device. It uses a subset of the capabilities of the PPC bus AB121
protocol.
PPC Address Mapping
The PHB will map either PCI memory space or PCI I/O space into PPC
address space using four programmable map decoders. These decoders
provide windows into the PCI bus from the PPC bus. The most significant
Product picture display
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reminder
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