Emerson 12P2532X152 KJ3222X1-BA1 CE4003S2B1 system module spare parts
Technical data of product parameters
The PCC includes a DMA Channel Controller (DMAC) to move
data between the SCSI chip and memory. The DMA channel 12P2532X152 KJ3222X1-BA1 CE4003S2B1
features a 32-bit address pointer for data transfers, a 32-bit pointer
for the command chaining table, and a 24-bit byte counter.
Because of its 8-bit to 32-bit data bus width conversion, the chip
moves SCSI data at rates up to 1.5MB/second while using less than
25 percent of the local bus bandwidth when doing a DMA to local
DRAM.The DMAC has two initiation modes: direct and command 12P2532X152 KJ3222X1-BA1 CE4003S2B1
chaining (scatter-gather).
In the direct mode, the data address pointer and the byte count are
loaded into the chip.
In the command chaining mode, a table of data addresses and byte
counts is placed in local RAM and the address of the table is loaded
into the chip. The chip walks through the addresses and byte counts
from the local RAM to move each block of data as indicated by the
table. Scatter-gather operations are supported by command
chaining. 12P2532X152 KJ3222X1-BA1 CE4003S2B1
The PCC can DMA to/from local DRAM and VMEbus memory
only. Any other access results in a local bus time-out.
The DMAC is always in one of three operational states: idle state,
table walk state, or data transfer state. The DMA sequences through
the three depending upon the contents of the DMA control register
which is initialized by the MPU. The DMAC starts out from reset in the idle state. It stays in the idle
state until the DMAC is enabled (DMAEN set to 1). It returns to the
idle state when the DMAC has completed the requested operations
(normally or with error). It does not leave the idle state again until
all error status bits are cleared and DMAEN is again set to
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Introduction to main products
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reminder
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