Emerson 1C31224G01 controller
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If the user is not passing data with the 1C31224G01interrupt, then this step is unnecessary and may be skipped. 3. Read the Interrupt 2 Sender ID FIFO at RFMCSRBase + offset $2C and place the value in the desired location. This value is the node ID of the source of the network interrupt. Provided that there are no additional network interrupts stored in the Sender ID 1C31224G01 , the act of reading this value will de-assert the Pending Network Interrupt 2 bit (Bit 01) in the LISR, which in turn de-asserts the LINT0 line. De-asserting the LINT0 line will de-assert the PCI interrupt. 4. Write a one (1) to the VINT_STAT register at UniverseIIBase + offset $314. This will de-assert the VMEbus interrupThe Universe II has a DMA controller for high performance data transfer between the RFM and VMEbus. It is 1C31224G01operated through a series of registers that control the source and destination for the data, length of the transfer and the transfer protocol to be used. The DMA registers reside in a block starting at offset $200. They describe a single DMA transfer: where to transfer data from; where to transfer data to; how much data to transfer; and the transfer attributes to use on the VMEbus. A final register contains status and control information for the transfer. While the DMA is active, the registers are locked against any 1C31224G01changes so that any writes to the registers will have no impact.The source and destination addresses for the DMA reside in two registers: the DMA PCI bus Address Register (DLA register, ), and the DMA VMEbus Address Register (DVA register in ). The determination of which is the source address, and which is the destination is made by the L2V bit in the DCTL register (Table 3-12 on page 71). When set, the DMA transfers data from the PCI to the VMEbus. Hence DLA becomes the PCI source register and DVA becomes the VMEbus destination register. When cleared, the DMA
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