Emerson CE3007 KJ2005X1-BA1 12P4375X042 module card
Technical data of product parameters
The PCC has a 32-bit register which is CE3007 KJ2005X1-BA1 12P4375X042 used to hold data that is
transferred between the SCSI bus and the local bus. Bits 0-3
indicate the status of each byte of the holding register (byte
position in longword: UU = upper upper; UM = upper middle;
LM = lower middle; LL = lower lower). When a bit is low, the
corresponding byte is empty. When a bit is high, the
corresponding byte is full. These bits are cleared when the DMA
controller is disabled. These bits are cleared by reset.
Bits 4-7 The DMA address and byte counters may be incremented by 1,
2, 3, or 4. When the DMA counters are incremented, the CE3007 KJ2005X1-BA1 12P4375X042
increment value is saved in these bits. Only one of the 4 bits is
set. These bits are cleared when the DMA controller is disabled.
These bits are cleared by reset. When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
Bit 6 This bit indicates the current state of the ABORT switch. When
this bit is low, the ABORT switch is not pressed. When this bit is
high, the ABORT switch is pressed.
Bit 7 When this bit is high, an abort interrupt is being generated at
Level 7. This bit is edge sensitive and it is set on the leading
edge of interrupt enable and abort. This bit is cleared when a 1
is written to it or when the interrupt is disabled. When cleared, CE3007 KJ2005X1-BA1 12P4375X042
it remains cleared until the next leading edge of interrupt enable
and abort. This bit is cleared by reset. These bits program the interrupt level that the serial ports
generate. Level 0 does not generate an interrupt.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. CE3007 KJ2005X1-BA1 12P4375X042
Bit 4 This bit controls the vector source. When this bit is low, the
interrupt status/id vector comes from the serial chip. When this
bit is high, the interrupt status/id vector comes from the PCC.
Bit 7 When this bit is high, a serial port interrupt is being generated
at the level programmed in bits 0-2. This bit is level sensitive
and it is active when interrupt enable and serial port interrupt
are active.
Product picture display
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Introduction to main products
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reminder
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