FOXBORO P0926MX communication module

FOXBORO P0926MX communication module

Technical data of product parameters

Setting the MASD16 bit forces the P0926MX to perform only
D8 and D16 data transfers on the VMEbus. Clearing the
MASD16 bit allows D8, D16, and D32 transfer capability on the
VMEbus when the MC68030 accesses in the range below
$F0000000. (Accesses to VMEbus locations above $F0000000 are
always restricted to D8/D16 regardless of the MASD16 bit.)
This bit is cleared by P0926MX
Bit 1 If either the MASA24 bit is set, or the MC68030 accesses the
VMEbus in the range below $1000000, the master drives one of
the standard (24-bit) address modifier codes during VMEbus
cycles (unless the master is configured to use the master address
modifier register as described in the Master Address Modifier
Register section in this chapter). The specific standard AM code
is determined from the levels that the MC68030 drives on the
three function code lines during the cycle, as shown in the table
below. This bit is cleared by P0926MX
Bit 2 If either the MASA16 bit is set, or the MC68030 accesses the
VMEbus in the range above $FFFF0000, a short (16-bit) AM
code is used regardless of the state of the MASA24 bit (unless
the master is configured to use the master address modifier
register as described in the Master Address Modifier Register
section in this chapter). The specific short AM code is
determined from the levels that the MC68030 drives on the
three function code lines during the cycle, as shown in the
following table. This bit is cleared by P0926MX This bit is cleared by SYSRESET. It should remain cleared.
Bit 5 Setting the MASWP bit speeds up MC68030 writes to the
VMEbus. However, it should be used with caution. When
MASWP (Master Write Posting) is set, MC68030 write cycles to
the VMEbus are acknowledged by the VMEchip, before they
have actually finished on the VMEbus. The VMEchip finishes
the write cycles on its own, allowing the MC68030 to continue
with new cycles. If the SLVEN bit is cleared (slave disabled), the
VMEchip acknowledges VME writes even before it has obtained
VMEbus mastership. If the SLVEN bit is set, then it waits until it
has obtained VMEbus mastership. This bit is cleared by
SYSRESET.

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