IC693CMM321 communication module

IC693CMM321 communication module

Technical data of product parameters

The DRAM is accessible by the MC68030, PCC, LANCE, and
VMEbus. It is specifically optimized for the MC68030. IC693CMM321
The parity feature is not implemented on the MVME147-010.
The MVME147 has parity check which operates in one of three user
selectable modes.
In mode 1, no parity checking is performed and the DRAM operates
at maximum speed. IC693CMM321
In mode 2, parity checking is performed for all bus masters and the
DRAM operates at maximum speed when the MC68030 is bus
master. When a parity error occurs in mode 2 and the MC68030 is
the local bus master, the bus error signal is not activated during the
current cycle. The bus error is activated during all subsequent
MC68030 DRAM cycles. All other bus masters are notified of parity
errors during the current cycle, consequently their DRAM access
time increases by 1 clock. IC693CMM321
In mode 3, parity checking is performed for all bus masters and
parity errors are reported during the current cycle. In this mode, the
DRAM access time is extended by one clock cycle to allow for parity
checking.When the PCC needs to transfer data, it requests local bus
mastership from the GCC multiport arbiter. When the PCC has
been granted local bus mastership, it executes one bus cycle and
then releases bus mastership. If a parity error is detected during a
PCC to DRAM read cycle, a bus error is returned to the PCC. When the VMEbus map decoder detects an onboard DRAM select, the VMEchip requests local bus mastership from the GCC
multiport arbiter. When the GCC multiport arbiter has granted
local bus mastership, a DRAM read or write cycle happens and the
VMEchip activates the DTACK* (or BERR* if parity is enabled and
a parity error occurs) signal on the VMEbus.
If the VMEbus master is executing a read-modify-write cycle
(RMC) to the DRAM, the GCC multiport arbiter allows rearbitration of the local bus between the read and write portions of
the sequence. It does not, however, allow the MC68030 to regain
local bus mastership until both the read and write cycles have
occurred to the DRAM.

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