Kollmorgen E33CHA-LNN-NS-00 PLC module programmable controller

Kollmorgen E33CHA-LNN-NS-00 PLC module programmable controller

Technical data of product parameters

The SX counter is implemented by a 24 bit up/down counter (23 bit + sign). The E33CHA-LNN-NS-00
counter is implemented by a 24 bit up-counter.
The SX and SR counters accumulates pulses during a measurement period. The
measurement period can be determined in two different ways (user selectable):
By a measurement interval timer.
By the coincidence comparator function.
With the first method is a measurement interval for each channel defined by the user E33CHA-LNN-NS-00
in increments of 1 ms from 1 to 2.700 ms. By changing the measurement interval
the user can select a suitable filter time (integration time) with respect to the
application’s requirements.
With the second method is the measure interval controlled by the coincidence E33CHA-LNN-NS-00
function, that is, a measurement interval is started when a coincidence is detected.
Next coincidence terminates the measurement interval, and starts a new
measurement interval.
At the end of each measurement period are the SX and SR registers is updated with E33CHA-LNN-NS-00
the value of the SX and SR counters. The CPU reads the content in the SX and SR
registers and calculates a frequency value.
It is possible to synchronize frequency measurements between the two channels,
that is, the measurement period from one of the channels is then used by both
channels.
A frequency sample condition can be specified by the user. When a sample
condition is fulfilled is the value in the SX and SR registers “freezed”.

Product picture display

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