OMACO GF0-57CQD-002 Control System Module

OMACO GF0-57CQD-002 Control System Module

Technical data of product parameters

result, it is not possible to capture the values of all four timers at a given instance in GF0-57CQD-002
time. However, by setting this bit to “1”, all four timer outputs will be latched only on
reads to the Timer 1 & 2 Current Count Register (TMRCCR12). Therefore, to capture
the current count of all four timers at the same time, perform a read to the TMRCCR12
first (with a 32-bit read), followed by a read to TMRCCR3 and TMRCCR4. The first
read (to the TMRCCR12 register) causes all four timer values to be latched at the same
time. The subsequent reads to the TMRCCR3 and TMRCCR4 registers do not latch GF0-57CQD-002
new count values, allowing the count of all timers at the same instance in time to be
obtained.
The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by Timer 1.
Writing to this register, located at offset 0x30 from the address in BAR2, causes the
interrupt from Timer 1 to be cleared. This can also be done by writing a “0” to the GF0-57CQD-002
appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).
This register is write only and the data written is irrelevantThe Timer 2 IRQ Clear (T2IC) register is used to clear an interrupt caused by Timer 2.
Writing to this register, located at offset 0x34 from the address in BAR2, causes the
interrupt from Timer 2 to be cleared. This can also be done by writing a “0” to the
appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).
This register is write only and the data written is irrelevant.

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