PSCCM22AAN 16418-5312 PLC DCS module

PSCCM22AAN 16418-5312 PLC DCS module

Technical data of product parameters

These bits program the interrupt level the tick timer generates PSCCM22AAN 16418-5312 .
Because level 0 does not generate an interrupt, this level is
intended for polling software. These bits are cleared by reset.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
Bit 7 When this bit is high, a tick timer interrupt is being generated at
the level programmed in bits 0-2. This bit is edge sensitive and it
is set by a carry out of the tick timer when interrupts are PSCCM22AAN 16418-5312
enabled. This bit is cleared when a 1 is written to it or when the
interrupt is disabled. When cleared, it remains cleared until the
next carry out. This bit is cleared by reset. When this bit is low, the timer is disabled and the counter is
loaded with the preload value. When the bit is high, the counter
is enabled and it starts counting up if the counter enable bit (bit
1) is high. This bit is cleared by reset.
Bit 1 When this bit is low, the counter is stopped. The counter value is
not changed when the counter is stopped and started with this
bit. When this bit is high, the counter is enabled. This bit is
cleared by reset.
Bit 2 The overflow counter is cleared by writing a 1 to this bit.
Bits 4-7 These read only bits are the output of the overflow counter. The
overflow counter is incremented each time the tick timer rolls
over. These bits are cleared by reset. Bit set and clear instructions should not be used on this PSCCM22AAN 16418-5312
interrupt control register. Because an interrupt is
cleared by writing a 1 to the status bit and the status bit
is a 1 to indicate a pending interrupt, the read-modifywrite sequence may clear a pending interrupt. These bits program the interrupt level the tick timer generates.
Because level 0 does not generate an interrupt, this level is
intended for polling software. These bits are cleared by reset.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
Bit 7 When this bit is high, a tick timer interrupt is being generated at
the level programmed in bits 0-2. This bit is edge sensitive and it
is set by a carry out of the tick timer when interrupts are
enabled. This bit is cleared when a 1 is written to it or when the
interrupt is disabled. When cleared, it remains cleared until the
next carry out. This bit is cleared by reset.

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Introduction to main products

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reminder

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