VE3008 12P6381X022 KJ2005X1-MQ1 PLC/DCS module in stock
Technical data of product parameters
1. Bit set and clear instructions should not be used on
this control register. Because the WD time-out bit is
cleared by writing a 1 to it and the status bit is a 1 to VE3008 12P6381X022 KJ2005X1-MQ
indicate a time-out, the read-modify-write sequence
may clear the WD time-out.
2. The recommended use of this register is first to set all
the control bits as desired but with the enable bit low.
Next, write this register again with the same data, but
this time with the enable bit high; this access will
actually start the watchdog timer. When this bit is low, the watchdog timer is disabled. When this VE3008 12P6381X022 KJ2005X1-MQ
bit is high, the watchdog timer is enabled, and increments each
time tick timer 1 rolls over. This bit is cleared by reset.
Bit 1 The watchdog timer is cleared by writing a 1 to this bit.
Bit 2 When this bit is low, the watchdog timer does not activate the
reset signal if a time-out occurs. When this bit is high, the
watchdog timer activates the reset signal if a time-out occurs.
This bit is cleared by reset. This bit should only be set if the
MVME147 is system controller.
Bit 3 This bit is set if the watchdog timer times out. This bit is cleared
by writing a 1 to it. This bit is cleared by reset.
Bits 4-7 These bits set the watchdog limit. When the watchdog timer
value is equal to the watchdog limit, the WdTO bit (bit 3) is set.
These bits are cleared by reset.Bit set and clear instructions should not be used on this VE3008 12P6381X022 KJ2005X1-MQ control register. Because the interrupt is cleared by
writing a 1 to the status bit and the status bit is a 1 to
indicate a pending interrupt, the read-modify-write
sequence may clear a pending interrupt. When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
Bit 4 When this bit is low, the rising edge of ACK* generates an
interrupt. When this bit is high, the falling edge of ACK*
generates an interrupt. This bit is cleared by reset.
Bit 5 When interrupts are enabled, this bit is set by the rising or
falling edge of ACK* as selected by bit 4. This bit is edge
sensitive and is cleared by writing a 1 to it or when printer
interrupts are disabled. VE3008 12P6381X022 KJ2005X1-MQ
Bit 6 When interrupts are enabled, this bit is set by the falling edge of
FAULT*. This bit is edge sensitive and is cleared by writing a 1
to it or when printer interrupts are disabled.
Bit 7 When this bit is high, a printer interrupt is being generated at
the level programmed in bits 0-2. This bit is the OR of bits 5 and
6. This bit is cleared by reset.
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Introduction to main products
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